The present invention relates generally to digital data stream and more specifically to a digital multiplexor design. Digital multiplexors can be used to select an output between two or more input data streams. They may also be used as a parallel to serial converter by sequentially selecting between each of the inputs. They are typically built from an arrangement of digital building blocks, And gates and inverters. The technology used to build the gates and inverters are typically bipolar transistors (BJTs) for speeds below 100 MHz, heterojunction bipolar transistors (HBTs) for speeds up to a GH/z and, gallium arsenide high electron-mobility transistor field effect transistors (GaAs HEMT FETs). The present state of the art digital chip employing GaAs HEMT FETs can run at 10 GB/s reliably and, at extreme costs ($100 k or more) 20 GB/s.
Current digital multiplexor technology is described in the following U.S. patents, the disclosures of which are incorporated herein by reference:
U.S. Pat. No. 5,627,991 issued to Hose,
U.S. Pat. No. 5,862,408 issued to Dey;
U.S. Pat. No. 6,065,070 issued to Johnson; and
U.S. Pat. No. 5,635,857 issued to Flora.
The Hose reference discloses a cache memory with a two to one multiplexor assembly to process data chunks. Communication systems employing analog or digital radio frequency (RF) hardware has been capable of frequencies above 44 GHz Q-band) for many years. Recent advances in optical technologies has allowed for development of digital system test beds exceeding 100 GB/s. A need has arisen for high data rate sources and receivers to test systems at more than 10 GB/s.